Model the connections. Realize the board.

Parts own Ports, Interfaces connect those ports, and Items describe the power, signals, or data that flow through them. Ports can decompose into connector pins, while Linkages represent physical cables, harnesses, or other interconnect hardware.

The Wiring view traverses connectivity rather than only hierarchy. It lays out part and linkage regions, connector blocks, pins, and interface tracks so engineers can inspect and edit how the system connects. This logical architecture complements detailed circuit nets; Davinci does not imply that every system interface automatically becomes a PCB net.

BuildSchematic creates declarative circuit source only after resolving the required symbol and footprint candidates. Exact selections, required references, pin maps, and package assignments act as hard generation constraints rather than suggestions.

The active Schematic view combines an INDEX of components and nets, a CODE editor, a graphical canvas, and DRC / LINT diagnostics. Add parts, connect pins, create signal or power nets, rotate and mirror components, and compile the same underlying circuit source.

BuildLayout creates the initial board outline, stackup, placement, and routing policy. Focused tools then update placement, outline geometry, constraints, board rules, and routing intent without regenerating unrelated authored work.

Preview routing is designed for interactive iteration and can return a valid partial route. A board should only be presented as fabrication-ready after a full compile confirms complete routing, current realization, and clean physical checks.

Davinci schematic lint evaluates the compiled netlist. It reports issues such as single-pin and undriven nets, power-ground shorts, incomplete interface pairs, floating power inputs, and missing or unresolved footprints. Warning-only findings remain advisory.

Board DRC is performed through KiCad on the realized PCB. It checks physical board rules, unconnected items, routing and pour findings, and fabrication blockers. The schematic panel is intentionally described as connectivity lint, not as KiCad ERC.

CompileCircuitCad creates a board-level CAD artifact from the current layout, including the outline, cutouts, drills, placed component bodies, and optional visual or fused copper. ViewCircuit3D renders that exact requested variant for inspection.

Generated mechanical interfaces expose stable board seats, mounting holes, component anchors, connector axes, and footprint drills to assemblies. Components without detailed models may use simplified representations, and the UI reports a partial result instead of overstating completeness.

BuildPorts, BuildInterfaces, and BuildInterconnect create connector hierarchies, resolve their leaf terminals, route interface continuity, and generate a physical linkage between distinct endpoints. Use them to model board-to-board, board-to-sensor, and harness-level connectivity above the component netlist.

BuildComponent can author a KiCad symbol, footprint, or matched pair from a datasheet. It verifies the package before symbol generation, enforces authoritative pin count and pin definitions for complex devices, validates physical footprint geometry, and saves neither file until the complete requested result passes.

SearchSymbols and SearchFootprints search bundled KiCad libraries and uploaded project assets. Results include exact circuit-language usage, pin information, package assignments, and project object identifiers so downstream generation can re-resolve and authorize the chosen asset.

The PCB view exposes Stackup and Rules controls for copper layers, board thickness, dielectric and finish, routing widths and clearances, fabrication limits, mask and paste, and silkscreen and text. Rule changes invalidate generated routing so the board can be proven again under the updated constraints.

Declarative layout source captures net classes, differential pairs, routing order, escape and fanout policy, and copper pours. Engineers can also author traces and vias directly. Generated routing remains distinguishable from deliberate copper so incremental edits and repours do not silently erase design intent.

The Circuit Table view groups the compiled schematic into Type, Value, Count, Reference, and Designators. Export the result as CSV or XLSX for review and procurement workflows while retaining the source circuit as the underlying engineering artifact.

Board exports include the realized .kicad_pcb, Gerber archives with drill output, and SVG or PNG views. Schematic exports include PDF, SVG, PNG, tabular formats, and KiCad-style netlist XML. Davinci does not currently claim pick-and-place or arbitrary KiCad project import.

A .spice code object can bind to a Circuit, combine its compiled netlist with analysis and plot directives, and execute through ngspice. This is a backend runtime workflow—not in-browser execution—and is available only when backend code execution is enabled for the deployment.