pour GND (B.Cu)
D1.1 SIPM_BIAS
D1.2 SIPM_ANODE1
D2.1 SIPM_BIAS
D2.2 SIPM_ANODE2
D3.1 SIPM_BIAS
D3.2 SIPM_ANODE3
D4.1 SIPM_BIAS
D4.2 SIPM_ANODE4
J1.1 +3V3
J1.2 GND
J1.3 SIPM_BIAS
J1.4 MCU_TX
J1.5 MCU_RX
J1.6 SIPM_CH4
J1.7 VREF
J1.8 unassigned
D1.1 SIPM_BIAS
D1.2 SIPM_ANODE1
D2.1 SIPM_BIAS
D2.2 SIPM_ANODE2
D3.1 SIPM_BIAS
D3.2 SIPM_ANODE3
D4.1 SIPM_BIAS
D4.2 SIPM_ANODE4
J1.1 +3V3
J1.2 GND
J1.3 SIPM_BIAS
J1.4 MCU_TX
J1.5 MCU_RX
J1.6 SIPM_CH4
J1.7 VREF
J1.8 unassigned
D1.1 SIPM_BIAS
D1.2 SIPM_ANODE1
D2.1 SIPM_BIAS
D2.2 SIPM_ANODE2
D3.1 SIPM_BIAS
D3.2 SIPM_ANODE3
D4.1 SIPM_BIAS
D4.2 SIPM_ANODE4
J1.1 +3V3
J1.2 GND
J1.3 SIPM_BIAS
J1.4 MCU_TX
J1.5 MCU_RX
J1.6 SIPM_CH4
J1.7 VREF
J1.8 unassigned
D1.1 SIPM_BIAS
D1.2 SIPM_ANODE1
D2.1 SIPM_BIAS
D2.2 SIPM_ANODE2
D3.1 SIPM_BIAS
D3.2 SIPM_ANODE3
D4.1 SIPM_BIAS
D4.2 SIPM_ANODE4
J1.1 +3V3
J1.2 GND
J1.3 SIPM_BIAS
J1.4 MCU_TX
J1.5 MCU_RX
J1.6 SIPM_CH4
J1.7 VREF
J1.8 unassigned
D1.1 SIPM_BIAS
D1.2 SIPM_ANODE1
D2.1 SIPM_BIAS
D2.2 SIPM_ANODE2
D3.1 SIPM_BIAS
D3.2 SIPM_ANODE3
D4.1 SIPM_BIAS
D4.2 SIPM_ANODE4
J1.1 +3V3
J1.2 GND
J1.3 SIPM_BIAS
J1.4 MCU_TX
J1.5 MCU_RX
J1.6 SIPM_CH4
J1.7 VREF
J1.8 unassigned
D1.1 SIPM_BIAS
D1.2 SIPM_ANODE1
D2.1 SIPM_BIAS
D2.2 SIPM_ANODE2
D3.1 SIPM_BIAS
D3.2 SIPM_ANODE3
D4.1 SIPM_BIAS
D4.2 SIPM_ANODE4
J1.1 +3V3
J1.2 GND
J1.3 SIPM_BIAS
J1.4 MCU_TX
J1.5 MCU_RX
J1.6 SIPM_CH4
J1.7 VREF
J1.8 unassigned
D1.1 SIPM_BIAS
D1.2 SIPM_ANODE1
D2.1 SIPM_BIAS
D2.2 SIPM_ANODE2
D3.1 SIPM_BIAS
D3.2 SIPM_ANODE3
D4.1 SIPM_BIAS
D4.2 SIPM_ANODE4
J1.1 +3V3
J1.2 GND
J1.3 SIPM_BIAS
J1.4 MCU_TX
J1.5 MCU_RX
J1.6 SIPM_CH4
J1.7 VREF
J1.8 unassigned
D1.1 SIPM_BIAS
D1.2 SIPM_ANODE1
D2.1 SIPM_BIAS
D2.2 SIPM_ANODE2
D3.1 SIPM_BIAS
D3.2 SIPM_ANODE3
D4.1 SIPM_BIAS
D4.2 SIPM_ANODE4
J1.1 +3V3
J1.2 GND
J1.3 SIPM_BIAS
J1.4 MCU_TX
J1.5 MCU_RX
J1.6 SIPM_CH4
J1.7 VREF
J1.8 unassigned
D1.1 SIPM_BIAS
D1.2 SIPM_ANODE1
D2.1 SIPM_BIAS
D2.2 SIPM_ANODE2
D3.1 SIPM_BIAS
D3.2 SIPM_ANODE3
D4.1 SIPM_BIAS
D4.2 SIPM_ANODE4
J1.1 +3V3
J1.2 GND
J1.3 SIPM_BIAS
J1.4 MCU_TX
J1.5 MCU_RX
J1.6 SIPM_CH4
J1.7 VREF
J1.8 unassigned
D1.1 SIPM_BIAS
D1.2 SIPM_ANODE1
D2.1 SIPM_BIAS
D2.2 SIPM_ANODE2
D3.1 SIPM_BIAS
D3.2 SIPM_ANODE3
D4.1 SIPM_BIAS
D4.2 SIPM_ANODE4
J1.1 +3V3
J1.2 GND
J1.3 SIPM_BIAS
J1.4 MCU_TX
J1.5 MCU_RX
J1.6 SIPM_CH4
J1.7 VREF
J1.8 unassigned
D1.1 SIPM_BIAS
D1.2 SIPM_ANODE1
D2.1 SIPM_BIAS
D2.2 SIPM_ANODE2
D3.1 SIPM_BIAS
D3.2 SIPM_ANODE3
D4.1 SIPM_BIAS
D4.2 SIPM_ANODE4
J1.1 +3V3
J1.2 GND
J1.3 SIPM_BIAS
J1.4 MCU_TX
J1.5 MCU_RX
J1.6 SIPM_CH4
J1.7 VREF
J1.8 unassigned
D1.1 SIPM_BIAS
D1.2 SIPM_ANODE1
D2.1 SIPM_BIAS
D2.2 SIPM_ANODE2
D3.1 SIPM_BIAS
D3.2 SIPM_ANODE3
D4.1 SIPM_BIAS
D4.2 SIPM_ANODE4
J1.1 +3V3
J1.2 GND
J1.3 SIPM_BIAS
J1.4 MCU_TX
J1.5 MCU_RX
J1.6 SIPM_CH4
J1.7 VREF
J1.8 unassigned
D1.1 SIPM_BIAS
D1.2 SIPM_ANODE1
D2.1 SIPM_BIAS
D2.2 SIPM_ANODE2
D3.1 SIPM_BIAS
D3.2 SIPM_ANODE3
D4.1 SIPM_BIAS
D4.2 SIPM_ANODE4
J1.1 +3V3
J1.2 GND
J1.3 SIPM_BIAS
J1.4 MCU_TX
J1.5 MCU_RX
J1.6 SIPM_CH4
J1.7 VREF
J1.8 unassigned
D1.1 SIPM_BIAS
D1.2 SIPM_ANODE1
D2.1 SIPM_BIAS
D2.2 SIPM_ANODE2
D3.1 SIPM_BIAS
D3.2 SIPM_ANODE3
D4.1 SIPM_BIAS
D4.2 SIPM_ANODE4
J1.1 +3V3
J1.2 GND
J1.3 SIPM_BIAS
J1.4 MCU_TX
J1.5 MCU_RX
J1.6 SIPM_CH4
J1.7 VREF
J1.8 unassigned
D1.1 SIPM_BIAS
D1.2 SIPM_ANODE1
D2.1 SIPM_BIAS
D2.2 SIPM_ANODE2
D3.1 SIPM_BIAS
D3.2 SIPM_ANODE3
D4.1 SIPM_BIAS
D4.2 SIPM_ANODE4
J1.1 +3V3
J1.2 GND
J1.3 SIPM_BIAS
J1.4 MCU_TX
J1.5 MCU_RX
J1.6 SIPM_CH4
J1.7 VREF
J1.8 unassigned
D1.1 SIPM_BIAS
D1.2 SIPM_ANODE1
D2.1 SIPM_BIAS
D2.2 SIPM_ANODE2
D3.1 SIPM_BIAS
D3.2 SIPM_ANODE3
D4.1 SIPM_BIAS
D4.2 SIPM_ANODE4
J1.1 +3V3
J1.2 GND
J1.3 SIPM_BIAS
J1.4 MCU_TX
J1.5 MCU_RX
J1.6 SIPM_CH4
J1.7 VREF
J1.8 unassigned
D1.1 SIPM_BIAS
D1.2 SIPM_ANODE1
D2.1 SIPM_BIAS
D2.2 SIPM_ANODE2
D3.1 SIPM_BIAS
D3.2 SIPM_ANODE3
D4.1 SIPM_BIAS
D4.2 SIPM_ANODE4
J1.1 +3V3
J1.2 GND
J1.3 SIPM_BIAS
J1.4 MCU_TX
J1.5 MCU_RX
J1.6 SIPM_CH4
J1.7 VREF
J1.8 unassigned
D1.1 SIPM_BIAS
D1.2 SIPM_ANODE1
D2.1 SIPM_BIAS
D2.2 SIPM_ANODE2
D3.1 SIPM_BIAS
D3.2 SIPM_ANODE3
D4.1 SIPM_BIAS
D4.2 SIPM_ANODE4
J1.1 +3V3
J1.2 GND
J1.3 SIPM_BIAS
J1.4 MCU_TX
J1.5 MCU_RX
J1.6 SIPM_CH4
J1.7 VREF
J1.8 unassigned
D1.1 SIPM_BIAS
D1.2 SIPM_ANODE1
D2.1 SIPM_BIAS
D2.2 SIPM_ANODE2
D3.1 SIPM_BIAS
D3.2 SIPM_ANODE3
D4.1 SIPM_BIAS
D4.2 SIPM_ANODE4
J1.1 +3V3
J1.2 GND
J1.3 SIPM_BIAS
J1.4 MCU_TX
J1.5 MCU_RX
J1.6 SIPM_CH4
J1.7 VREF
J1.8 unassigned
D1.1 SIPM_BIAS
D1.2 SIPM_ANODE1
D2.1 SIPM_BIAS
D2.2 SIPM_ANODE2
D3.1 SIPM_BIAS
D3.2 SIPM_ANODE3
D4.1 SIPM_BIAS
D4.2 SIPM_ANODE4
J1.1 +3V3
J1.2 GND
J1.3 SIPM_BIAS
J1.4 MCU_TX
J1.5 MCU_RX
J1.6 SIPM_CH4
J1.7 VREF
J1.8 unassigned
D1.1 SIPM_BIAS
D1.2 SIPM_ANODE1
D2.1 SIPM_BIAS
D2.2 SIPM_ANODE2
D3.1 SIPM_BIAS
D3.2 SIPM_ANODE3
D4.1 SIPM_BIAS
D4.2 SIPM_ANODE4
J1.1 +3V3
J1.2 GND
J1.3 SIPM_BIAS
J1.4 MCU_TX
J1.5 MCU_RX
J1.6 SIPM_CH4
J1.7 VREF
J1.8 unassigned
D1.1 SIPM_BIAS
D1.2 SIPM_ANODE1
D2.1 SIPM_BIAS
D2.2 SIPM_ANODE2
D3.1 SIPM_BIAS
D3.2 SIPM_ANODE3
D4.1 SIPM_BIAS
D4.2 SIPM_ANODE4
J1.1 +3V3
J1.2 GND
J1.3 SIPM_BIAS
J1.4 MCU_TX
J1.5 MCU_RX
J1.6 SIPM_CH4
J1.7 VREF
J1.8 unassigned
D1.1 SIPM_BIAS
D1.2 SIPM_ANODE1
D2.1 SIPM_BIAS
D2.2 SIPM_ANODE2
D3.1 SIPM_BIAS
D3.2 SIPM_ANODE3
D4.1 SIPM_BIAS
D4.2 SIPM_ANODE4
J1.1 +3V3
J1.2 GND
J1.3 SIPM_BIAS
J1.4 MCU_TX
J1.5 MCU_RX
J1.6 SIPM_CH4
J1.7 VREF
J1.8 unassigned
D1.1 SIPM_BIAS
D1.2 SIPM_ANODE1
D2.1 SIPM_BIAS
D2.2 SIPM_ANODE2
D3.1 SIPM_BIAS
D3.2 SIPM_ANODE3
D4.1 SIPM_BIAS
D4.2 SIPM_ANODE4
J1.1 +3V3
J1.2 GND
J1.3 SIPM_BIAS
J1.4 MCU_TX
J1.5 MCU_RX
J1.6 SIPM_CH4
J1.7 VREF
J1.8 unassigned
D1.1 SIPM_BIAS
D1.2 SIPM_ANODE1
D2.1 SIPM_BIAS
D2.2 SIPM_ANODE2
D3.1 SIPM_BIAS
D3.2 SIPM_ANODE3
D4.1 SIPM_BIAS
D4.2 SIPM_ANODE4
J1.1 +3V3
J1.2 GND
J1.3 SIPM_BIAS
J1.4 MCU_TX
J1.5 MCU_RX
J1.6 SIPM_CH4
J1.7 VREF
J1.8 unassigned
D1.1 SIPM_BIAS
D1.2 SIPM_ANODE1
D2.1 SIPM_BIAS
D2.2 SIPM_ANODE2
D3.1 SIPM_BIAS
D3.2 SIPM_ANODE3
D4.1 SIPM_BIAS
D4.2 SIPM_ANODE4
J1.1 +3V3
J1.2 GND
J1.3 SIPM_BIAS
J1.4 MCU_TX
J1.5 MCU_RX
J1.6 SIPM_CH4
J1.7 VREF
J1.8 unassigned
D1.1 SIPM_BIAS
D1.2 SIPM_ANODE1
D2.1 SIPM_BIAS
D2.2 SIPM_ANODE2
D3.1 SIPM_BIAS
D3.2 SIPM_ANODE3
D4.1 SIPM_BIAS
D4.2 SIPM_ANODE4
J1.1 +3V3
J1.2 GND
J1.3 SIPM_BIAS
J1.4 MCU_TX
J1.5 MCU_RX
J1.6 SIPM_CH4
J1.7 VREF
J1.8 unassigned
D1.1 SIPM_BIAS
D1.2 SIPM_ANODE1
D2.1 SIPM_BIAS
D2.2 SIPM_ANODE2
D3.1 SIPM_BIAS
D3.2 SIPM_ANODE3
D4.1 SIPM_BIAS
D4.2 SIPM_ANODE4
J1.1 +3V3
J1.2 GND
J1.3 SIPM_BIAS
J1.4 MCU_TX
J1.5 MCU_RX
J1.6 SIPM_CH4
J1.7 VREF
J1.8 unassigned
D1.1 SIPM_BIAS
D1.2 SIPM_ANODE1
D2.1 SIPM_BIAS
D2.2 SIPM_ANODE2
D3.1 SIPM_BIAS
D3.2 SIPM_ANODE3
D4.1 SIPM_BIAS
D4.2 SIPM_ANODE4
J1.1 +3V3
J1.2 GND
J1.3 SIPM_BIAS
J1.4 MCU_TX
J1.5 MCU_RX
J1.6 SIPM_CH4
J1.7 VREF
J1.8 unassigned
D1.1 SIPM_BIAS
D1.2 SIPM_ANODE1
D2.1 SIPM_BIAS
D2.2 SIPM_ANODE2
D3.1 SIPM_BIAS
D3.2 SIPM_ANODE3
D4.1 SIPM_BIAS
D4.2 SIPM_ANODE4
J1.1 +3V3
J1.2 GND
J1.3 SIPM_BIAS
J1.4 MCU_TX
J1.5 MCU_RX
J1.6 SIPM_CH4
J1.7 VREF
J1.8 unassigned
D1.1 SIPM_BIAS
D1.2 SIPM_ANODE1
D2.1 SIPM_BIAS
D2.2 SIPM_ANODE2
D3.1 SIPM_BIAS
D3.2 SIPM_ANODE3
D4.1 SIPM_BIAS
D4.2 SIPM_ANODE4
J1.1 +3V3
J1.2 GND
J1.3 SIPM_BIAS
J1.4 MCU_TX
J1.5 MCU_RX
J1.6 SIPM_CH4
J1.7 VREF
J1.8 unassigned
pour VREF (F.Cu)
D1.1 SIPM_BIAS
D1.2 SIPM_ANODE1
D2.1 SIPM_BIAS
D2.2 SIPM_ANODE2
D3.1 SIPM_BIAS
D3.2 SIPM_ANODE3
D4.1 SIPM_BIAS
D4.2 SIPM_ANODE4
U1.1 SIPM_CH1
U1.2 SIPM_ANODE1
U1.3 VREF
U1.4 GND
U1.5 VREF
U1.6 SIPM_ANODE2
U1.7 SIPM_CH2
U1.8 +3V3
R1.1 SIPM_CH1
R1.2 SIPM_ANODE1
R2.1 SIPM_CH2
R2.2 SIPM_ANODE2
R11.1 +3V3
R11.2 SIPM_CH1
C1.1 SIPM_CH1
C1.2 SIPM_ANODE1
C2.1 SIPM_CH2
C2.2 SIPM_ANODE2
C9.1 VREF
C9.2 GND
U2.1 SIPM_CH3
U2.2 SIPM_ANODE3
U2.3 VREF
U2.4 GND
U2.5 VREF
U2.6 SIPM_ANODE4
U2.7 SIPM_CH4
U2.8 +3V3
R3.1 SIPM_CH3
R3.2 SIPM_ANODE3
R4.1 SIPM_CH4
R4.2 SIPM_ANODE4
C3.1 SIPM_CH3
C3.2 SIPM_ANODE3
C4.1 SIPM_CH4
C4.2 SIPM_ANODE4
U3.1 SIPM_CH1
U3.2 SIPM_CH3
U3.3 SIPM_CH2
U3.4 GND
U3.5 MCU_TX
U3.6 MCU_RX
U3.7 SIPM_CH4
U3.8 +3V3
C10.1 +3V3
C10.2 GND
R9.1 +3V3
R9.2 VREF
R10.1 VREF
R10.2 GND
J1.1 +3V3
J1.2 GND
J1.3 SIPM_BIAS
J1.4 MCU_TX
J1.5 MCU_RX
J1.6 SIPM_CH4
J1.7 VREF
J1.8 unassigned
D1
D2
D3
D4
U1
R1
R2
R11
C1
C2
C9
U2
R3
R4
C3
C4
U3
C10
R9
R10
J1
warning: Silkscreen overlap
warning: Silkscreen overlap